PCB Controlled Impedance & Trace Width Calculator
Based on the IPC-2141 field solver formulas — enter trace geometry to get impedance, or enter a target impedance (50 Ω / 75 Ω / 90 Ω / 100 Ω …) to get the precise trace width.
| Trace Width (mil) | Trace Width (mm) | Impedance (Ω) |
|---|
Unit conversions: 1 oz/ft² = 1.4 mil = 35.6 µm · 1 in = 25.4 mm · W, H, T, S must share the same unit inside the formulas.
Notes: ① Formulas are first-order (IPC-2141) and assume a homogeneous dielectric — controlled-impedance production is verified against your fab's stackup with impedance test coupons on every panel. ② Solder mask over outer-layer traces typically lowers Z₀ by roughly 2–5%. ③ Keep W/H within 0.1–20 for best accuracy; very narrow traces on tall dielectrics drift toward coplanar-waveguide behaviour. ④ For design reference — validate with your fabricator before production.
Frequently Asked Questions
1. How accurate are the results from this calculator?
The calculator uses the IPC-2141 empirical formulas, which typically agree with a 2D field solver to within about ±5–10% for standard stack-ups. Real boards add uncertainty the formulas cannot model: FR-4 Dk varies between laminate batches and even across a panel, and copper etching pulls the finished trace width. Treat the calculated width as an engineering starting point, and confirm it with an impedance test coupon on the production panel. LEADHUI supplies coupon test reports with every controlled-impedance order.
2. What dielectric constant should I enter?
Use the design Dk at your actual operating frequency, not the datasheet cover number. FR-4 datasheets are usually specified at 1 MHz (~4.5); at 1 GHz the effective value typically drops to around 4.2–4.3. For high-speed boards use a low-Dk material such as Megtron, RO4350B or RT5880 — quick presets are built into the calculator. If your stack-up is critical, ask your laminate vendor for the Dk vs. frequency curve and we will confirm the final numbers against your coupon test results.
3. Why does solder mask lower the impedance?
Solder mask has εr ≈ 3.2–3.8, and covering the trace raises the effective dielectric constant around it — especially on outer-layer microstrip lines. The typical effect is a 2–5% impedance drop compared with bare copper. This is normal: your coupon should be tested with the solder mask in place, in the same state as production. If you need tighter control, tell us which state to test and we will manage the solder mask opening per layer.
4. The calculator says my target impedance is not reachable — what should I do?
The IPC formulas only have a solution for a limited range of trace widths. To raise impedance: increase the dielectric height H, use thinner copper, or switch to a lower-Dk material. To lower impedance: widen the trace or reduce H. A common case is 50 Ω on a 2-mil core — impossible in practice; the calculator tells you which direction to adjust. Send us your target impedance and layer count and we will propose a manufacturable stack-up.
5. Do I really need an impedance test coupon?
Yes — it is th
e only proof that the finished panel meets your target. A coupon carries representative traces measured by TDR (time-domain reflectometry) after fabrication, with the finished stack-up including copper and solder mask. LEADHUI includes coupon test reports with controlled-impedance orders as standard, so you can verify 50 Ω ±10% (or your specified tolerance) before assembly.
