PCB Via Current Calculator
IPC-2221 based — work out how much current a plated through-hole can carry, its resistance and voltage drop, or reverse-size the hole and the number of parallel vias your power net needs.
| Hole (mm) | Hole (mil) | Area (mm²) | Imax / via (A) | Resistance (mΩ) | Vias for I |
|---|
Current capacity: I = k · ΔT0.44 · A0.725 (IPC-2221), with A in mil², k = 0.048 for external conductors and 0.024 for internal ones. A via is wrapped in FR-4 and dissipates heat poorly, so the internal coefficient (k = 0.024) is the safe default.
Resistance: R = ρ·L / A, where ρ₂₀ = 1.72×10⁻⁸ Ω·m with a temperature coefficient of 0.00393/°C, and L is the via length (≈ board thickness for a through-hole). Voltage drop and power loss use I / N per via.
Unit conversions: 1 mil = 0.0254 mm = 25.4 µm · 1 oz/ft² = 35 µm of surface copper (barrel plating is specified separately) · Δ°F = Δ°C × 9/5 · °F = °C × 9/5 + 32.
Notes: ① IPC-6012 Class 2 requires ≥ 20 µm average barrel plating (≥ 25 µm for Class 3); high aspect-ratio holes are thinner at the barrel centre — confirm the finished minimum with your fabricator. ② Parallel vias do not share current perfectly: this tool applies a 0.75 sharing derate whenever N > 1, so total capacity = Ivia × N × 0.75. ③ Aspect ratios above 8:1 (board thickness / hole diameter) are difficult to plate uniformly. ④ IPC-2221 is deliberately conservative; IPC-2152 or a thermal simulation is more accurate for high-current designs. ⑤ Results exclude filled / plugged vias, thermal relief and solder-mask effects — for design reference only, validate by measurement before production.
Frequently Asked Questions
Which standard and formula does this calculator use?
IPC-2221. A standard via is a hollow copper cylinder, so its conducting cross-section is the annular barrel wall: A = π · t · (D + t), where D is the finished hole diameter and t is the barrel plating thickness. The current formula is I = k · ΔT^0.44 · A^0.725 with A in mil², k = 0.048 for external conductors and 0.024 for internal ones, and ΔT the allowed temperature rise. The calculator also reports resistance, voltage drop and power loss, and can reverse-solve the minimum hole diameter for a target current.
Why is the internal thermal model the default?
Because a via is surrounded by FR-4, not air. FR-4 is a thermal insulator, so heat generated in the barrel can only spread into the laminate and adjacent copper planes; it cannot convect to the surroundings the way a surface trace can. The internal coefficient k = 0.024 is therefore the conservative choice — the external value k = 0.048 would roughly double the predicted capacity. Switch to External only when the via is genuinely exposed to airflow or tied to a large heatsinking plane.
Which matters more: hole diameter or plating thickness?
Plating thickness, usually. Cross-section is A = π · t · (D + t), and the barrel wall is very thin — a 0.3 mm hole with 25 µm plating has only 0.0255 mm² of copper, far less than a 0.3 mm wide 1 oz surface trace. Doubling the plating nearly doubles the area; enlarging the hole helps far less per unit of board area. IPC-6012 Class 2 requires 20 µm average barrel copper (25 µm for Class 3), and high aspect-ratio holes are thinner at the barrel centre — always confirm the finished minimum with your fabricator.
How is via resistance calculated, and does board thickness matter?
R = ρ·L/A, where ρ is copper resistivity (1.72×10⁻⁸ Ω·m at 20 °C, corrected for operating temperature), L is the via length — approximately the board thickness for a through-hole — and A is the plated cross-section. A typical 0.3 mm via with 25 µm plating through a 1.6 mm board is about 1.08 mΩ. Board thickness does not change current capacity, which depends on cross-section, but it does increase resistance, voltage drop and power loss. It also raises the aspect ratio: above 8:1 the barrel is hard to plate uniformly.
How many parallel vias do I need for a high-current net?
Do not simply divide by the single-via rating. Manufacturing tolerances and layout asymmetry mean current is not shared equally, so this calculator applies a 0.75 sharing derate whenever more than one via is used: total capacity = I per via × N × 0.75. For example, a 0.3 mm / 25 µm via rated about 0.95 A at a 10 °C rise needs 8 vias to carry 5 A with a +10% margin. Spread the array evenly along the current path rather than clustering it, and keep the traces feeding each via wide enough.
What temperature rise and safety margin should I use?
10 °C with +10% margin is the recommended default. A 5 °C rise is more conservative for sealed enclosures, high ambient temperatures and high-reliability boards; 20–30 °C is acceptable only for intermittent loads. The margin inflates the design current before the calculator solves for the minimum hole or the number of vias, so the result already includes it. For continuous full load in a hot enclosure, choose +20%.
Does the calculator cover filled vias, microvias and IPC-2152?
No — it models a standard hollow plated through-hole. Copper-filled or conductively plugged vias have a larger effective cross-section and will carry more current; laser microvias are blind and much shorter, so enter the dielectric layer thickness as the via length rather than the full board thickness. IPC-2221 is an older, deliberately conservative empirical model; IPC-2152 and thermal simulation agree better with measurements on modern stack-ups. Treat the result as a safe lower bound and validate high-current paths by current-loading a test coupon or with thermal imaging. LEADHUI can build coupons with your production stack-up.